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Table 8 - Address and protocol encoding
Figure 35 - I 2 C address and protocol setting
I2C Address
R APS (Ω) 1)
Protocol
Controller EEPROM
2)
820
2700
5600
PMBus?
0xB0
0xB2
0xB4
0xA0
0xA2
0xA4
3.3V
8200
15000
27000
56000
180000
PSMI
0xB6
0xB0
0xB2
0xB4
0xB6
0xA6
0xA0
0xA2
0xA4
0xA6
ADC
12k
APS
R APS
1)
2)
E12 resistor values, use max 5% resistors, see also Figure 35.
The LSB of the address byte is the R/W bit.
8.14 CONTROLLER AND EEPROM ACCESS
The controller and the EEPROM in the power supply share the same I 2 C bus physical layer (see Figure 36 ). An I2C driver
device assures logic level shifting (3.3/5 V) and a glitch-free clock stretching. The driver also pulls the SDA/SCL line to nearly
0 V when driven low by the DSP or the EEPROM providing maximum flexibility when additional external bus repeaters are
needed. Such repeaters usually encode the low state with different voltage levels depending on the transmission direction.
The DSP will automatically set the I 2 C address of the EEPROM with the necessary offset when its own address is changed /
set. In order to write to the EEPROM, first the write protection needs to be disabled by sending the appropriate command to
the DSP. By default the write protection is on.
The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply.
Figure 36 - I 2 C Bus to DSP and EEPROM
SDA
APS
Address & Protocol Selection
SDA i
SCL
SCL i
WP
DSP
Protection
EEPROM
Addr
8.15 EEPROM PROTOCOL
The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read
commands are defined, it is recommended to use the single byte write / read commands.
WRITE
The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte
with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the
bus should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory.
S Address W A
Data Address
A
Data
A
P
READ
The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data
address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with
the data byte at the specified location.
S Address W A
Data Address
A
BCD.00040_AG Sep-11-2013
S Address R
A
15
Data
nA P
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